The invention relates to a charge pump for generating high voltages for integrated semiconductor circuits, having a plurality of pump stages each having at least one power transistor for generating a pump voltage on a power path. The power transistor has a freely connectable bulk terminal, with which a well structure of the power transistor can be held at a predetermined potential via a well charging path that is substantially separate from the power path. In order to generate the predetermined potential, a first and a second well charging transistor are switched into the well charging path. The well charging transistors are connected in series, their junction point being connected to the bulk terminal of the power transistor and the outer terminals of the series circuit being connected in parallel with the outputs of the power transistor. A pump capacitor is connected between two pump stages in each case.
In the context of this description, the term xe2x80x9chigh voltagesxe2x80x9d refers to voltages whose magnitude is greater than a positive and/or negative supply voltage Vdd/Vss that is present at the relevant integrated semiconductor circuit. Such high positive and also negative voltages are required in most modern semiconductor circuits. This relates, in particular, to those circuits which comprise memories such as, for example, EEPROMs, DRAMs, FRAMs, etc. Furthermore, specific applications such as e.g. contactless systems such as mobile phones, chip cards, smartcards or wire-free devices appertaining to medical technology lead to ever smaller designs (0.25 xcexcm, 0.18 xcexcm) in the semiconductor technology of the integrated circuits, so that it is necessary also to reduce the supply voltages further and further (2.5 volts, 1.8 volts, 1 volt) and, consequently, charge pumps are required which must be evermore powerful in order to generate the high voltages mentioned in the introduction. Since the applications are generally battery-operated, it is desirable, moreover, for the total energy consumption to be kept as low as possible in order to enable a long operating duration.
In a semiconductor process, the basic elements are constructed from p- and n-doped regions with different doping, thereby producing a number of pn junctions and pnp and npn transistors. In a standard application, generally only positive voltages with a maximum level of Vdd and negative voltages with a minimum level of Vss are used with the basic elements (PMOS, NMOS, R, C), the standard situation being that the n-type well of the PMOS transistors is connected to Vdd and the p-type well of the NMOS transistors is connected to Vss. Consequently, in accordance with the specification, the pn junctions are expediently always reverse-biased and the pnp and npn transistors are always in the off state. However, as soon as voltages which differ from the voltages Vdd and Vss are required, special circuit concepts are necessary in order, with the basic elements then no longer connected up in a specification-forming manner, to keep the pn junctions and the pnp and npn transistors turned off. Thus, in an n-type well process, for example, the n-type well, which contains at least one p-doped channel of a PMOS transistor, is not permitted to be charged negatively since the n-type well/p-type substrate junction constitutes a forward-biased pn diode. Correspondingly, the well potential is not permitted to become lower than the voltage potential at a contact set into the well (positive base-emitter voltage, pnp transistor, p+-type contact/n-type well/p-type substrate).
Firstly, two prior art charge pumps which have been used previously in attempts to avoid these problems will be explained with reference to FIGS. 5 to 8. FIG. 5 shows the circuit of a charge pump for negative output voltages, while FIG. 7 illustrates a corresponding circuit for positive output voltages. FIGS. 6 and 8 in each case show a timing scheme for the driving of the circuit in accordance with FIG. 5 and FIG. 7, respectively.
The circuits are each composed of N+1 pump stages x which are connected in a series and together form a power path. A supply voltage Vdd is present at the input of the circuit, from which supply voltage the pump voltage Vpmp is generated, which charges a charging capacitor Cload at the output of the charge pump. In this case, the switching elements of a pump stage x are respectively designated by the same second index x.
The charge transport to the load capacitor Cload is effected via a plurality of power transistors M1x and pump capacitors Cpx in each pump stage x, which are alternately turned on and turned off and alternately charge and discharge the pump capacitors. For the driving of a power transistor M1x, each pump stage x furthermore has a control transistor M2x and a boost capacitor Cbx, which form a control circuit. An external clock generator (not illustrated) feds to those terminals of the pump and boost capacitors which are designated by F1 to F4 in FIGS. 5 and 7. The clock signals, in each case designated identically, in accordance with FIGS. 6 and 8, respectively. These illustrations are intended only to make it clear at what instance signals with a high or low level are present at the individual capacitors Cbx, Cpx of two successive pump stages.
In detail, during a first clock phase t1, a clock signal with a low level is present at the pump capacitor Cp2 of the second stage and the boost capacitor Cb1 of the first stage, and a clock signal with a high level is present at the pump capacitor Cp1 of the first stage and the boost capacitor Cb2 of the second stage.
In this case, the power transistor M11 of the first stage carries the required charge, while the control transistor M21 of the first stage serves for precharging the gate of the power transistor during the first clock phase t1.
During a second clock phase t2, wherein a clock signal with a low level is fed to the pump capacitor Cp1 of the first stage and to the boost capacitor Cb2 of the second stage and a clock signal with a high level is present at the pump capacitor Cp2 of the second stage and the boost capacitor Cb1 of the first stage, the control transistor M21 of the first stage is closed, and the potential at the gate of the power transistor M11 is reduced by at most the supply voltage Vdd by means of a boost pulse at the boost capacitor Cb1. As a result, the power transistor M11 opens particularly well, and the voltage drop across this transistor M11 can be minimized.
However, a first problem here is that this mechanism operates reliably only for as long as, in the first clock phase, the gate-source voltage (Vgs voltage) of the control transistor M21 (which corresponds to the drain-source voltage across the power transistor M11) is greater than the threshold voltage of the PMOS transistors used therefor. If the Vgs voltage is less than the threshold voltage of the PMOS transistors, then the gate of the power transistor M11 is no longer precharged, so that the transistor M11 does not remain in the on state and the pump fails.
A second problem arises when the pump is spontaneously discharged to zero volts by a discharging element at the output of the circuit. This is because charges then remain on the gates of the power transistors M1x, and cause a relatively high negative or positive potential there. The consequence of this is that all the power transistors M1x are greatly turned on and connect the input of the pump circuit to its output. If the supply voltage is too low, after the pump has been switched on again, the charges on the gates of the power transistors can no longer be removed. This means that the short circuit between the input and the output of the charge pump is maintained and the pump can no longer run up.
Finally, a third problem occurs by virtue of the fact that the NMOS or PMOS transistors, with their bulk terminal (p-type or n-type well), must be kept at zero volts or be per se at zero volts, in order that the well-substrate pn junction is not turned on. This implies a rising substrate control factor with rising positive or negative potential at the transistors. In detail, this means that the threshold voltage arises, to be precise to a greater extent in a p-type well process than in an n-type well process. As a result, the output voltage is limited by the last transistor in the chain (at the output, i.e. maximum potential) in a manner dependent on the temperature and the technology used.
It is accordingly an object of the invention to provide a charge pump for generating high voltages for semiconductor circuits, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the three above-mentioned problems essentially do not occur, i.e. with which a reliable pump operation for generating relatively high output voltages is possible even at low operating voltages.
With the foregoing and other objects in view there is provided, in accordance with the invention, a charge pump for generating high voltages for integrated semiconductor circuits, comprising:
a plurality of pump stages and a pump capacitor connected between respective pump stages;
each of the pump stages having at least one power transistor for generating a pump voltage on a power path thereof, the power transistor having a well structure, a well charging path substantially separate from the power path, and a freely connectable bulk terminal via which the well structure can be held at a predetermined potential through the well charging path;
first and second well charging transistors connected into the well charging path for generating the predetermined potential;
the well charging transistors forming a series circuit having a node connected to the bulk terminal of the power transistor and outer terminals connected in parallel with the power transistor; and
first and second boost capacitors connected to receive clock signals for controlling the charge pump, the first and second well charging transistors each having a control terminal respectively connected to the first and second boost capacitors.
In other words, the objects of the invention are achieved by a charge pump of the type mentioned in the introduction which is distinguished in particular by the fact that the power transistor has a freely connectable bulk terminal, with which a well structure of the power transistor can be held at a predetermined potential via a well charging path that is substantially separate from the power path.
In accordance with an added feature of the invention, first and second control transistors are connected to be acted upon by the first and second boost capacitors and forming a control circuit driving the power transistor.
In accordance with an additional feature of the invention, there is provided a device for generating the clock signals for driving the boost capacitors and the pump capacitors, and wherein, in order to switch off the charge pump, the clock signals at the boost capacitors initially remain activated for removing charges stored in the charge pump.
In accordance with another feature of the invention, the power transistor is an NMOS transistor formed as a triple well transistor with a first n-type well and a second p-type well in the first well, and the bulk terminal is connected to a p+-doped region in the second well.
In accordance with a concomitant feature of the invention, the power transistor is a PMOS transistor with an n-type well, and the bulk terminal is connected to at least one n+-doped region in the well.
Accordingly, in order to generate the predetermined potential, a first and a second charging transistor are switched into the charging path. In this case, the charging transistors are connected in series, their junction point being connected to the bulk terminal of the power transistor and the outer terminals of the series circuit being connected in parallel with the outputs of the power transistor. Furthermore, the control terminal of the first and second charging transistors is in each case connected to a first or second boost capacitor, at each of which clock signals for controlling the charge pump are present.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a charge pump for generating high voltages for semiconductor circuits, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.